हिंदी में: प्रोसेसर अंदर से कैसे काम करता है — इंस्ट्रक्शन साइकिल, पाइपलाइनिंग और कैश मेमोरी।
Organization vs architecture
- Computer architecture – attributes visible to the programmer: instruction set, data types, addressing modes, number of registers.
- Computer organization – how those features are implemented: control signals, memory technology, interfaces.
Digital logic foundations
Computers are built from logic gates: AND, OR, NOT, NAND, NOR, XOR, XNOR. NAND and NOR are universal gates — any circuit can be built using only one of them.
- Combinational circuits – output depends only on current inputs (adders, multiplexers, decoders, encoders).
- Sequential circuits – output also depends on stored state (flip-flops: SR, D, JK, T; registers; counters).
Boolean expressions are simplified with Boolean algebra and Karnaugh maps (K-maps).
The instruction cycle
- Fetch – read the instruction from memory at the address in the Program Counter (PC).
- Decode – the control unit works out what the instruction means.
- Execute – the ALU or other units perform the operation.
- Store / write back – save the result to a register or memory.
Important registers: PC (next instruction address), IR (current instruction), MAR (memory address register), MDR/MBR (memory data register), accumulator, and general-purpose registers.
Instruction formats and addressing modes
Instructions can have zero, one, two or three address fields. Addressing modes describe where the operand is:
| Mode | Operand is… |
|---|---|
| Immediate | In the instruction itself |
| Register | In a register |
| Direct | At the memory address given |
| Indirect | At the address stored at the given address |
| Indexed / base | At base address + index/offset |
| Relative | At PC + offset (used in branches) |
Control unit design
- Hardwired control – fast, built from logic circuits; hard to modify (typical of RISC).
- Microprogrammed control – control signals stored as microinstructions in control memory; flexible (common in CISC).
RISC vs CISC
| RISC | CISC |
|---|---|
| Few, simple, fixed-length instructions | Many, complex, variable-length instructions |
| Most instructions execute in one cycle | Instructions may take many cycles |
| Load/store architecture, many registers | Memory operands allowed in many instructions |
| Easy to pipeline | Harder to pipeline |
| ARM, RISC-V, MIPS | x86 |
Pipelining
Pipelining overlaps the stages of several instructions, like an assembly line. A classic 5-stage pipeline is IF → ID → EX → MEM → WB. Ideally a k-stage pipeline approaches a speed-up of k.
Hazards reduce that speed-up: – Structural – two instructions need the same hardware. – Data – an instruction needs a result not yet produced (fixed with forwarding/bypassing or stalls). – Control – branches change the flow (fixed with branch prediction).
Memory organization and cache
Caches exploit locality of reference: temporal (recently used data is used again) and spatial (nearby data is used soon).
- Mapping: direct-mapped, fully associative, set-associative.
- Replacement: LRU, FIFO, random.
- Write policies: write-through, write-back.
- Effective access time = hit ratio × cache time + (1 − hit ratio) × miss penalty (one common simplified form).
Input/Output
- Programmed I/O – the CPU repeatedly checks device status (polling).
- Interrupt-driven I/O – the device interrupts the CPU when ready.
- DMA (Direct Memory Access) – a DMA controller moves blocks of data between memory and the device without the CPU handling every byte.
Performance
CPU time = Instruction count × CPI (cycles per instruction) × clock cycle time. Amdahl’s law reminds us that the overall speed-up is limited by the part of a program that cannot be improved or parallelised.
Quick revision
- NAND and NOR are universal gates.
- Fetch → Decode → Execute → Write back.
- Three hazards: structural, data, control.
- DMA moves data without constant CPU involvement.